Verilog
  url
  pkgsrc
  and2
  7seg
    7seg.v
    test.v
    compile
    exec
  4 bit counter
  16bit counter

software
Last Update: "2014/05/12 22:26:34 makoto"

16bit counter

/* 16 bit counter */
module counter (clk, reset, count);
    input clk, reset;
    output [14:0] count;
    reg [14:0] count;
    always @(negedge clk or posedge reset )
         if (reset) 
              count <= 4'b0000;
         else
               count <= count + 1'b1;
endmodule // counter



module TEST;
   reg clk;
   reg reset;
   wire [14:0] count;

   counter one(clk, reset, count);
   always #10 clk <= ~clk; 
 
   initial begin
      clk   = 0;
      reset = 1;
      $monitor( "%t: %b%b", $time,  count, clk);
      #1   reset = 0;
      #2560 $finish;
   end
endmodule
modena@makoto 22:24:29/140512(..verilog/16-bit_counter)% iverilog 16bit-counter.v modena@makoto 22:24:35/140512(..verilog/16-bit_counter)% ./a.out |head 0: 0000000000000000 10: 0000000000000001 20: 0000000000000010 30: 0000000000000011 40: 0000000000000100 50: 0000000000000101 60: 0000000000000110 70: 0000000000000111 80: 0000000000001000 90: 0000000000001001
x
Last Update: Wed, 01 Apr 2015 02:38:26 GMT 1.66 2008/03/08