Index: sys/arch/macppc/macppc/cpu.c
===================================================================
RCS file: /export/20050928/Repository/src/sys/arch/macppc/macppc/cpu.c,v
retrieving revision 1.3
diff -u -r1.3 cpu.c
--- sys/arch/macppc/macppc/cpu.c	29 Sep 2005 15:43:15 -0000	1.3
+++ sys/arch/macppc/macppc/cpu.c	2 Nov 2005 15:02:08 -0000
@@ -54,9 +54,11 @@
 #include <machine/trap.h>
 #include <machine/pte.h>
 #include <uvm/uvm_page.h>
+#include "spr.h"
 
 int cpumatch(struct device *, struct cfdata *, void *);
 void cpuattach(struct device *, struct device *, void *);
+static void cpu_probe_speed(struct cpu_info *);
 
 static void ohare_init(void);
 int cpu_spinup(void *);
@@ -143,7 +145,7 @@
 	switch (id) {
 	case 0:
 		identifycpu(model);
-		printf(": %s, ID %d (primary)\n", model, cpu_number());
+		printf(": %s, ID %d (primary) ", model, cpu_number());
 		break;
 	case 1:
 #ifdef MULTIPROCESSOR
@@ -162,6 +164,12 @@
 
 	powerpc_config_hid();
 
+	struct cpu_info *ci;
+	cpu_probe_speed(ci);
+	aprint_normal("%u.%02u MHz\n",
+		      ci->ci_khz / 1000, (ci->ci_khz / 10) % 100);
+
+
 	/* XXX */
 	if (vers == MPC750)
 		mpc750_disable_clkout();
@@ -531,3 +539,18 @@
 	return 1;
 }
 #endif /* MULTIPROCESSOR */
+void
+cpu_probe_speed(struct cpu_info *ci)
+{
+	uint64_t cps;
+
+	mtspr(SPR_MMCR0, MMCR0_FC);
+	mtspr(SPR_PMC1, 0);
+	mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES));
+	delay(100000);
+	cps = (mfspr(SPR_PMC1) * 10) + 4999;
+
+	mtspr(SPR_MMCR0, MMCR0_FC);
+
+	ci->ci_khz = cps / 1000;
+}
Index: sys/arch/macppc/macppc/spr.h
===================================================================
RCS file: sys/arch/macppc/macppc/spr.h
diff -N sys/arch/macppc/macppc/spr.h
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ sys/arch/macppc/macppc/spr.h	2 Nov 2005 14:52:43 -0000
@@ -0,0 +1,12 @@
+#ifndef SPR_H
+#define SPR_H
+
+#define  PMCN_CYCLES              1 /* Processor cycles */
+
+#define  SPR_MMCR0               0x3b8   /* .6. Monitor Mode Control Register 0 */
+#define  SPR_PMC1                0x3b9   /* .6. Performance Counter Register 1 */
+
+#define    MMCR0_PMC1SEL(x)        ((x) << 6) /* PMC1 selector */
+#define    MMCR0_FC                0x80000000 /* Freeze counters */
+
+#endif
Index: sys/arch/macppc/include/cpu.h
===================================================================
RCS file: /export/20050928/Repository/src/sys/arch/macppc/include/cpu.h,v
retrieving revision 1.2
diff -u -a -r1.2 cpu.h
--- sys/arch/macppc/include/cpu.h	29 Sep 2005 15:21:49 -0000	1.2
+++ sys/arch/macppc/include/cpu.h	2 Nov 2005 14:34:51 -0000
@@ -69,6 +69,7 @@
 	int ci_ddbsave[8];
 	int ci_disisave[4];
 	int ci_tickrem;
+	int ci_khz;
 #ifndef MULTIPROCESSOR
 	int ci_pad1[1];
 #endif