Index: lib/libc/arch/powerpc/string/bzero.S
===================================================================
RCS file: /cvs/cvsroot/src/lib/libc/arch/powerpc/string/bzero.S,v
retrieving revision 1.12
diff -u -r1.12 bzero.S
--- lib/libc/arch/powerpc/string/bzero.S	18 Jul 2013 12:20:41 -0000	1.12
+++ lib/libc/arch/powerpc/string/bzero.S	31 Aug 2013 03:21:10 -0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: bzero.S,v 1.12 2013/07/18 12:20:41 matt Exp $ */
+/*	$NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $ */
 
 /*-
  * Copyright (C) 2001	Martin J. Laubach <mjl@NetBSD.org>
@@ -32,7 +32,7 @@
 
 
 #if defined(LIBC_SCCS) && !defined(lint)
-__RCSID("$NetBSD: bzero.S,v 1.12 2013/07/18 12:20:41 matt Exp $")
+__RCSID("$NetBSD: bzero.S,v 1.11 2011/01/29 02:21:20 matt Exp $")
 #endif /* LIBC_SCCS && !lint */
 
 #ifdef _KERNEL
@@ -76,21 +76,17 @@
 		/* First find out cache line size */
 		mflr	%r9
 #ifdef PIC
-		bcl	20,31,1f
-1:		mflr	%r5
+		PIC_GOTSETUP(%r10)
 		mtlr	%r9
-		addis	%r5,%r5,cache_info+4-1b@ha
-		lwzu	%r9,cache_info+4-1b@l(%r5)
+		lwz	%r5,cache_info@got(%r10)
 #else
-		lis	%r5,cache_info+4@ha
-		lwzu	%r9,cache_info+4@l(%r5)
+		lis	%r5,cache_info@h
+		ori	%r5,%r5,cache_info@l
 #endif
-		lwz	%r10,cache_sh-(cache_info+4)(%r5)
-		cmpwi	%r9, -1
+		lwz	%r6, 4(%r5)
+		cmpwi	%r6, -1
 		bne+	cb_cacheline_known
 
-		addi	%r5, %r5, -4	/* point r5 @ beginning of cache_info */
-
 /*----------------------------------------------------------------------*/
 #define CTL_MACHDEP	7
 #define CPU_CACHELINE	1
@@ -176,25 +172,33 @@
 
 		cntlzw	%r6, %r9			/* compute shift value */
 		li	%r5, 31
-		subf	%r10, %r6, %r5
+		subf	%r5, %r6, %r5
 
 #ifdef PIC
 		mflr	%r9
-		bcl	20,31,1f
-1:		mflr	%r5
+		PIC_GOTSETUP(%r10)
 		mtlr	%r9
-
-		addis	%r5, %r5, cache_info+4-1b@ha
-		lwzu	%r9, cache_info+4-1b@l(%r5)
+		lwz	%r6, cache_sh@got(%r10)
+		stw	%r5, 0(%r6)
 #else
-		lis	%r5, cache_info+4@ha
-		lwzu	%r9, cache_info+4@l(%r5)
+		lis	%r6, cache_sh@ha
+		stw	%r5, cache_sh@l(%r6)
 #endif
-		stw	%r10, cache_sh-(cache_info+4)(%r5)
-
 /*----------------------------------------------------------------------*/
 /* Okay, we know the cache line size (%r9) and shift value (%r10) */
 cb_cacheline_known:
+#ifdef PIC
+		lwz	%r5, cache_info@got(%r10)
+		lwz	%r9, 4(%r5)
+		lwz	%r5, cache_sh@got(%r10)
+		lwz	%r10, 0(%r5)
+#else
+		lis	%r9, cache_info+4@ha
+		lwz	%r9, cache_info+4@l(%r9)
+		lis	%r10, cache_sh@ha
+		lwz	%r10, cache_sh@l(%r10)
+#endif
+
 #else /* _KERNEL */
 #ifdef	MULTIPROCESSOR
 		mfsprg	%r10, 0			/* Get cpu_info pointer */
@@ -367,7 +371,6 @@
 /*----------------------------------------------------------------------*/
 #ifndef _KERNEL
 		.data
-		.p2align 2
 cache_info:	.long	-1, -1, -1, -1
 cache_sh:	.long	0
 
Index: sys/arch/powerpc/oea/oea_machdep.c
===================================================================
RCS file: /cvs/cvsroot/src/sys/arch/powerpc/oea/oea_machdep.c,v
retrieving revision 1.65
diff -u -r1.65 oea_machdep.c
--- sys/arch/powerpc/oea/oea_machdep.c	4 Jul 2013 22:59:27 -0000	1.65
+++ sys/arch/powerpc/oea/oea_machdep.c	31 Aug 2013 03:21:10 -0000
@@ -95,6 +95,17 @@
  */
 static void trap0(void *);
 
+#if 1
+/* The work around for prep machine, which hung if the battable address 
+   pattern is xxx1 11xx .
+   To align struct battable in x 0000, say, 16bit boundary, suggested by kiyohara@ 
+   To make sure this fragment only to affect .bss, .section directive in and out
+   are here. */
+        __asm (".section .bss\n"
+               ".align 4\n"
+	       ".section .text\n"
+              );
+#endif
 /* XXXSL: The battable is not initialized to non-zero for PPC_OEA64 and PPC_OEA64_BRIDGE */
 struct bat battable[BAT_VA2IDX(0xffffffff)+1];