PCI configuration registers: Common header: 0x00: 0x25928086 0x00900007 0x03000003 0x00800000 Vendor Name: Intel (0x8086) Device Name: 82915GM/GMS,82910GML Integrated Graphics Device (0x2592) Command register: 0x0007 I/O space accesses: on Memory space accesses: on Bus mastering: on Special cycles: off MWI transactions: off Palette snooping: off Parity error checking: off Address/data stepping: off System error (SERR): off Fast back-to-back transactions: off Interrupt disable: off Status register: 0x0090 Interrupt status: inactive Capability List support: on 66 MHz capable: off User Definable Features (UDF) support: off Fast back-to-back capable: on Data parity error detected: off DEVSEL timing: fast (0x0) Slave signaled Target Abort: off Master received Target Abort: off Master received Master Abort: off Asserted System Error (SERR): off Parity error detected: off Class Name: display (0x03) Subclass Name: VGA (0x00) Interface: 0x00 Revision ID: 0x03 BIST: 0x00 Header Type: 0x00+multifunction (0x80) Latency Timer: 0x00 Cache Line Size: 0bytes (0x00) Type 0 ("normal" device) header: 0x10: 0xb0080000 0x00001801 0xc0000008 0xb0000000 0x20: 0x00000000 0x00000000 0x00000000 0x833810f7 0x30: 0x00000000 0x000000d0 0x00000000 0x0000010b Base address register at 0x10 type: 32-bit nonprefetchable memory base: 0xb0080000, not sized Base address register at 0x14 type: i/o base: 0x00001800, not sized Base address register at 0x18 type: 32-bit prefetchable memory base: 0xc0000000, not sized Base address register at 0x1c type: 32-bit nonprefetchable memory base: 0xb0000000, not sized Base address register at 0x20 not implemented(?) Base address register at 0x24 not implemented(?) Cardbus CIS Pointer: 0x00000000 Subsystem vendor ID: 0x10f7 Subsystem ID: 0x8338 Expansion ROM Base Address: 0x00000000 Capability list pointer: 0xd0 Reserved @ 0x38: 0x00000000 Maximum Latency: 0x00 Minimum Grant: 0x00 Interrupt pin: 0x01 (pin A) Interrupt line: 0x0b Capability register at 0xd0 type: 0x01 (Power Management, rev. 1.0) PCI Power Management Capabilities Register Capabilities register: 0x0022 Version: 1.1 PME# clock: off Device specific initialization: on 3.3V auxiliary current: self-powered D1 power management state support: off D2 power management state support: off PME# support D0: off PME# support D1: off PME# support D2: off PME# support D3 hot: off PME# support D3 cold: off Control/status register: 0x0000 Power state: D0 PCI Express reserved: off No soft reset: off PME# assertion: disabled PME# status: off Bridge Support Extensions register: 0x00 B2/B3 support: off Bus Power/Clock Control Enable: off Data register: 0x00 Device-dependent header: 0x40: 0x00000000 0x000000e0 0x21090009 0xa38be632 0x50: 0x0030000a 0xb8000019 0x00000000 0x5f800000 0x60: 0x00000000 0x00000000 0x00000000 0x00000000 0x70: 0x00000000 0x00000000 0x00000000 0x00000000 0x80: 0x00000000 0x00000000 0x00000000 0x00000000 0x90: 0x00000000 0x00000000 0x00000000 0x00000000 0xa0: 0x00000000 0x00000000 0x00000000 0x00000000 0xb0: 0x00000000 0x00000000 0x00000000 0x00000000 0xc0: 0x00000000 0x00000000 0x00000000 0x00000000 0xd0: 0x00220001 0x00000000 0x00000000 0x00000000 0xe0: 0x00000020 0x00000000 0x00000000 0x00000000 0xf0: 0x34640000 0x000000ff 0x00040000 0x00000000